This invention relates to electronic circuitry, and in particular to a method and structure for performing a floating point comparison, which is particularly useful for example, in a microprocessor or other digital computational circuits.
FIG. 1 is a block diagram of a typical prior art arithmetic circuit which is used for, among other things, performing floating point comparisons. As known in the art, a floating point comparison is the comparison between two floating point numbers in order to determine which, if either, is larger.
Referring to FIG. 1, the first floating point word to be compared is received on "A bus" 11a, and a second floating point word to be compared is received on "B bus" 11b. As known in the art, a typical floating point number contains 32 bits: 24 bits defining the mantissa, and 8 bits defining the exponent. Thus, the A bus and the B bus must each receive two 16 bit words in order to define the two floating point numbers to be compared. For certain operations, such as a floating point comparison of double precision numbers, 48 bits are required to define each double precision floating point number (40 bits to define a mantissa and 8 bits to define the exponent). In this event, three 16 bit words are required to fully define each double precision floating point number.
FIG. 2 shows a typical bit assignment of two 16 bit words for defining a floating point number. Since two 16 bit words are required to define each floating point number, the first word received on A bus 11a (FIG. 1) is denoted "RA" and the first 16 bit word received on B bus 11b (FIG. 1) is referred to as "RB". Similarly, the second 16 bit word received on A bus 11a is called "RA+1" and the second 16 bit word received on B bus 11b is called "RB+1". As shown in FIG. 2, RA and RB each define the 16 most significant mantissa bits, M0 through M15. The words RA+1 and RB+1 define in their 8 most significant bits, the 8 least significant bits of the mantissa, M16 through M23. The 8 least significant bits of words RA+1 and RB+1 define the 8 bits of the exponent, E0 through E7. In this manner, by receiving two consecutive words RA; RA+1 and RB; RB+1 on A bus 11a and B bus 11b, respectively, one 32 bit floating point number is received on each of the A bus and B bus for comparison.
However, since the structure of FIG. 1 contains only 16 bits wide paths, each half of the floating point numbers to be compared must be treated in separate steps, as is described more fully below.
Referring again to FIG. 1, A latch 12a and B latch 12b serve to latch the data received on A bus 11a and B bus 11b, respectively. A prelogic 13a and B prelogic 13b serve to preprocess the data in A latch 12a and B latch 12b, respectively, prior to application to arithmetic logic unit (ALU) 14. For example, A prelogic 13a and B prelogic 13b serve to mask out any desired bits, as is sometimes required prior to applying data to ALU 14 for certain operations. The data is thus applied to ALU 14, which performs a floating point subtraction operation in order to determine which is larger, the floating point number received on A bus 11a or the floating point number received on B bus 11b. The output of ALU 14 is applied to shifter 15 which serves to shift the result from ALU 14, if necessary for further operations.
In the prior art, in order to perform a floating point comparison, a floating point subtraction is performed. As is well known in the prior art, in order to perform a floating point subtraction, the two numbers must be aligned to insure that both numbers have the same exponent. This is the same as addition or subtraction of two numbers expressed in scientific notation, which can be added when both numbers are expressed with the same power of 10. Just like in the addition or subtraction of two numbers expressed in scientific notation, if the floating point numbers received on A bus 11a and B bus 11b do not have exponents which are identical, the numbers must be adjusted so that the exponents become identical. Once this is accomplished, the mantissa may simply be added or subtracted, while retaining the common exponents.
In the prior art, the algorithm of Table 1 is used to perform comparisons of two 32 bit floating point numbers, A and B.
TABLE 1 ______________________________________ Step 1 Subtract the exponents as represented by the 8 least significant bits of the 2 floating point numbers to be compared, and load the result in a temporary register: RTemp = (RA+1) [8:15] - (RB+1) [8:15] Step 2 Check the exponent flags to determine which number (A or B) has the larger exponent. If the two numbers A and B have the same exponent, the result stored in RTemp will be 0. If the floating point number A has a larger exponent than the floating point number B, then the result stored in RTemp will be positive. If the floating point number B has a larger exponent than the floating point number A, the result stored in RTemp will be negative. Step 3 Decide to adjust either floating point number A or floating point number B to cause floating point numbers A and B to have the same exponent in order that a floating point subtraction may be performed. Step 4 Perform a right shift of the 8 least significant bits of the mantissa of the smaller of floating point numbers RA+1 [0:7] and RB+1 [0:7]. Step 5 Perform an arithmetic right shift of the 16 most significant bits of the mantissa of the smaller of floating point numbers RA or RB. Step 6 Decrement the number stored in RTemp which defines the difference between the exponents of floating point numbers A and B. This number stored in RTemp thus defines the number of right shifts of the mantissa of the smaller of floating point numbers A or B required in order to cause both floating point numbers to have a common exponent. Step 7 Determine if the result stored in RTemp is equal to 0. If so, the exponents of the floating point numbers A and B have been equalized and the mantissas may be subtracted. If not, repeat steps 4 through 7. Step 8 Execute the subtraction to determine which, if either, of floating point numbers A and B is larger. ______________________________________
Since the mantissas of floating point numbers are 24 bits wide, a maximum of 23 shifts may be required to insure that the exponents of floating point numbers A and B are equal. Naturally, this is the worse case example, and in many instances a fewer number of shifts will be required. However, it is common that 10 or 15 right shifts are required in order to cause the A and B floating point numbers to have common exponents during the floating point subtraction operation. Furthermore, as seen above, performing the right shift of the least significant bits of the mantissa (step 4 above) and the right shift of the most significant bits of the mantissa (step 5 above) requires two separate micro instruction cycles. Thus, for each floating point comparison made by prior art techniques, a significant amount of instruction time is required, thereby causing each floating point comparison operation to severely impact the throughput a microprocessor or other structure employing the floating point comparison operation.